在verilog中将连线值转换为整数

wire [2:0] w = 3\'b101;

j=1;
for(i=0; i<=2; i=i+1)
begin
  a=a+(w[i]*j);   
  j=j*2;
end

integer my_int;
always @( w )
    my_int = w;

reg [127:0] huge_counter;
...
   always @(posedge clk)
      huge_counter <= huge_counter + 128\'h1;

wire [11:0] address;
reg  [ 7:0] memory [0:4095];
...
   assign read_data = memory[address];