在VHDL中将SystemC中的信号延迟指定为AFTER子句

process (clk)
   begin
      -- Updating my signal, out signal, in order to get result, but after a certain delay.
      signal1 <= '0' after 2 ns;

SC_CTOR(MyModule) {
   SC_METHOD(mymethod);
   sensitive << ....
}
void mymethod() {
   mysig = '0'; // HOW TO SAY AFTER 2 NS?????????
}

SC_THREAD

wait(2, SC_NS);

SC_METHOD

wait

SC_METHOD

write

mysig.write(0, 2*SC_NS);

mysig.Write(0, 2*ns);

mysig(2*ns) = 0;